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PCA9548A
8-channel I2C switch with reset
Rev. 01 -- 15 April 2005 Product data sheet
1. General description
The PCA9548A is an octal bi-directional translating switch controlled via the I2C-bus. The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. An active LOW reset input allows the PCA9548A to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the channels to be deselected as does the internal Power-on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9548A. This allows the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features
s s s s s s s s s s s s s s s 1-of-8 bi-directional translating switches I2C-bus interface logic; compatible with SMBus standards Active LOW reset input 3 address pins allowing up to 8 devices on the I2C-bus Channel selection via I2C-bus, in any combination Power-up with all switch channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low stand-by current Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 s Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA s Three packages offered: SO24, TSSOP24, and HVQFN24
Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
3. Ordering information
Table 1: Ordering information Tamb = -40 C to +85 C Type number PCA9548ABS PCA9548AD PCA9548APW Package Name HVQFN24 SO24 TSSOP24 Description Version plastic thermal enhanced very thin quad flat package; SOT616-1 no leads; 24 terminals; body 4 x 4 x 0.85 mm plastic small outline package; 24 leads; body width 7.5 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT137-1 SOT355-1
4. Marking
Table 2: Marking codes Topside mark 548A PCA9548AD PCA9548A Type number PCA9548ABS PCA9548AD PCA9548APW
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Product data sheet
Rev. 01 -- 15 April 2005
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
5. Block diagram
PCA9548A
SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
VSS VDD RESET
SWITCH CONTROL LOGIC
RESET CIRCUIT
SCL SDA
INPUT FILTER
A0 I2C-BUS CONTROL A1 A2
002aab202
Fig 1. Block diagram of PCA9548A
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Product data sheet
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
6. Pinning information
6.1 Pinning
A0 A1 RESET SD0 SC0 SD1 SC1 SD2 SC2
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 A2 20 SC7 19 SD7 18 SC6 17 SD6 16 SC5 15 SD5 14 SC4 13 SD4
002aab199
A0 A1 RESET SD0 SC0 SD1 SC1 SD2 SC2
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 A2 20 SC7 19 SD7 18 SC6 17 SD6 16 SC5 15 SD5 14 SC4 13 SD4
002aab200
PCA9548AD
PCA9548APW
SD3 10 SC3 11 VSS 12
SD3 10 SC3 11 VSS 12
Fig 2. Pin configuration for SO24
24 RESET
Fig 3. Pin configuration for TSSOP24
20 SDA
23 A1
SD0 SC0 SD1 SC1 SD2 SC2
1 2 3 4 5 6 SD4 10 SC4 11 SD5 12 7 8 9
22 A0
terminal 1 index area
19 SCL 18 A2 17 SC7 16 SD7 15 SC6 14 SD6 13 SC5
002aab201
PCA9548ABS
SD3
SC3
Transparent top view
Fig 4. Pin configuration for HVQFN24 (transparent top view)
9397 750 13297
VSS
21 VDD
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Product data sheet
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
6.2 Pin description
Table 3: Symbol A0 A1 RESET SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 VSS SD4 SC4 SD5 SC5 SD6 SC6 SD7 SC7 A2 SCL SDA VDD
[1]
Pin description Pin SO, TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 HVQFN 22 23 24 1 2 3 4 5 6 7 8 9 [1] 10 11 12 13 14 15 16 17 18 19 20 21 address input 0 address input 1 active LOW reset input serial data 0 serial clock 0 serial data 1 serial clock 1 serial data 2 serial clock 2 serial data 3 serial clock 3 supply ground serial data 4 serial clock 4 serial data 5 serial clock 5 serial data 6 serial clock 6 serial data 7 serial clock 7 address input 2 serial clock line serial data line supply voltage Description
HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.
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Product data sheet
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PCA9548A
8-channel I2C switch with reset
7. Functional description
Refer to Figure 1 "Block diagram of PCA9548A" on page 3.
7.1 Device address
Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9548A is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW.
1
1 fixed
1
0
A2
A1
A0 R/W
hardware selectable
002aab189
Fig 5. Slave address
The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation.
7.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9548A, which will be stored in the control register. If multiple bytes are received by the PCA9548A, it will save the last byte received. This register can be written and read via the I2C-bus.
channel selection bits (read/write) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7
002aab204
Fig 6. Control register
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Product data sheet
Rev. 01 -- 15 April 2005
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
7.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9548A has been addressed. The 2 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection.
Table 4: B7 X X X X X X X 0 1 B6 X X X X X X 0 1 X Control register: Write--channel selection; Read--channel status B5 X X X X X 0 1 X X B4 X X X X 0 1 X X X B3 X X X 0 1 X X X X B2 X X 0 1 X X X X X B1 X 0 1 X X X X X X B0 0 1 X X X X X X X Command channel 0 disabled channel 0 enabled channel 1 disabled channel 1 enabled channel 2 disabled channel 2 enabled channel 3 disabled channel 3 enabled channel 4 disabled channel 4 enabled channel 5 disabled channel 5 enabled channel 6 disabled channel 6 enabled channel 7 disabled channel 7 enabled
Remark: Multiple channels can be enabled at the same time. Example: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0, means that channels 7, 5, 4, 1 and 0 are disabled and channels 6, 3, and 2 are enabled. Care should be taken not to exceed the maximum bus capacitance. Default condition is all zeroes.
7.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tWL, the PCA9548A will reset its register and I2C-bus state machine and will deselect all channels. The RESET input must be connected to VDD through a pull-up resistor.
7.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9548A in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9548A register and I2C-bus state machine are initialized to their default states--all zeroes--causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device.
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Product data sheet
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PCA9548A
8-channel I2C switch with reset
7.5 Voltage translation
The pass gate transistors of the PCA9548A are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another.
5.0 Vo(sw) (V) 4.0
(1)
002aaa964
3.0
(2) (3)
2.0
1.0 2.0
2.5
3.0
3.5
4.0
4.5
5.5 5.0 VDD (V)
(1) maximum (2) typical (3) minimum
Fig 7. Pass gate voltage versus supply voltage
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the PCA9548A is only tested at the points specified in Section 11 "Static characteristics" of this data sheet). In order for the PCA9548A to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9548A supply voltage is 3.5 V or lower, so the PCA9548A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 14). More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches.
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Product data sheet
Rev. 01 -- 15 April 2005
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 8. Bit transfer
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 9).
SDA
SDA
SCL S START condition P STOP condition
SCL
mba608
Fig 9. Definition of START and STOP conditions
8.3 System configuration
A device generating a message is a `transmitter', a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 10).
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Product data sheet
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PCA9548A
8-channel I2C switch with reset
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C MULTIPLEXER
SLAVE
002aaa966
Fig 10. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 11. Acknowledgement on the I2C-bus
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Product data sheet
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
8.5 Bus transactions
Data is transmitted to the PCA9548A control register using the Write mode as shown in Figure 12.
slave address SDA S 1 1 1 0 A2 A1 A0 0 A B7 B6
control register B5 B4 B3 B2 B1 B0 A P
START condition
R/W
acknowledge from slave
acknowledge from slave STOP condition
002aab205
Fig 12. Write control register
Data is read from PCA9548A using the Read mode as shown in Figure 13.
slave address SDA S 1 1 1 0 A2 A1 A0 1 A B7 B6
control register B5 B4 B3 B2 B1
last byte
B0
NA
P
START condition
R/W
acknowledge from slave
no acknowledge from master STOP condition
002aab206
Fig 13. Read control register
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Product data sheet
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PCA9548A
8-channel I2C switch with reset
9. Application design-in information
VDD = 2.7 V to 5.5 V VDD = 3.3 V V = 2.7 V to 5.5 V
SDA SCL
SDA SCL
SD0 SC0
channel 0
V = 2.7 V to 5.5 V RESET I2C/SMBus master SD1 SC1 V = 2.7 V to 5.5 V
channel 1
SD2 SC2
channel 2
V = 2.7 V to 5.5 V
SD3 SC3
channel 3
PCA9548A
V = 2.7 V to 5.5 V
SD4 SC4
channel 4
V = 2.7 V to 5.5 V
SD5 SC5
channel 5
V = 2.7 V to 5.5 V
SD6 SC6
channel 6
V = 2.7 V to 5.5 V A2 A1 A0 VSS SD7 SC7
002aab203
channel 7
Fig 14. Typical application
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Product data sheet
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PCA9548A
8-channel I2C switch with reset
10. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V). [1] Symbol VDD VI II IO IDD ISS Ptot Tstg Tamb
[1]
Parameter supply voltage input voltage input current output current supply current ground supply current total power dissipation storage temperature operating ambient temperature
Conditions
Min -0.5 -0.5 -60 -40
Max +7.0 +7.0 20 25 100 100 400 +150 +85
Unit V V mA mA mA mA mW C C
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
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Product data sheet
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PCA9548A
8-channel I2C switch with reset
11. Static characteristics
Table 6: DC characteristics VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. See Table 7 on page 15 for VDD = 4.5 V to 5.5 V. [1] Symbol Supply VDD IDD Istb VPOR VIL VIH IOL IL Ci VIL VIH ILI Ci Pass gate Ron on-state resistance VDD = 3.0 V to 3.6 V; VO = 0.4 V; IO = 15 mA VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA Vo(sw) switch output voltage Vi(sw) = VDD = 3.3 V; Io(sw) = -100 A Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = -100 A Vi(sw) = VDD = 2.5 V; Io(sw) = -100 A Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = -100 A IL Cio
[1] [2]
Parameter supply voltage supply current standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance
Conditions
Min 2.3
Typ 30 0.1 1.6 6 9 15 2 11 16 1.9 1.5 3
Max 3.6 50 1 2.1 0.3VDD 6 +1 21 0.3VDD VDD + 0.5 +1 5 30 55 2.8 2.0 +1 5
Unit V A A V V V mA mA A pF V V A pF V V V V A pF
operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz standby mode; VDD = 3.6 V; no load; VI = VDD or VSS no load; VI = VDD or VSS
[2]
-0.5 0.7VDD
Input SCL; input/output SDA
VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS
3 6 -1 -0.5 0.7VDD
Select inputs A0 to A2, RESET
pin at VDD or VSS VI = VSS
-1 5 7 1.6 1.1 -1 -
leakage current input/output capacitance
VI = VDD or VSS VI = VSS
For operation between published voltage ranges, refer to the worst-case parameter in both ranges. VDD must be lowered to 0.2 V in order to reset part.
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Product data sheet
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
Table 7: DC characteristics VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. See Table 6 on page 14 for VDD = 2.3 V to 3.6 V. [1] Symbol Supply VDD IDD supply voltage supply current operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz standby mode; VDD = 5.5 V; no load; VI = VDD or VSS no load; VI = VDD or VSS
[2]
Parameter
Conditions
Min 4.5 -
Typ 65
Max 5.5 100
Unit V A
Istb VPOR VIL VIH IOL IIL IIH Ci VIL VIH ILI Ci Pass gate Ron Vo(sw)
standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current LOW-level input current HIGH-level input current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance on-state resistance switch output voltage
-0.5 0.7VDD
0.2 1.7 15 2 9 3.6 3
1 2.1 0.3VDD 6 1 1 21 0.3VDD VDD + 0.5 1 5 24 4.5 +1 5
A V V V mA mA A A pF V V A pF V V A pF
Input SCL; input/output SDA
VOL = 0.4 V VOL = 0.6 V VI = VSS VI = VDD VI = VSS
3 6 -1 -1 -0.5 0.7VDD
Select inputs A0 to A2, RESET
pin at VDD or VSS VI = VSS VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA Vi(sw) = VDD = 5.0 V; Io(sw) = -100 A Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = -100 A
-1 4 2.6 -1 -
IL Cio
[1] [2]
leakage current input/output capacitance
VI = VDD or VSS VI = VSS
For operation between published voltage ranges, refer to the worst-case parameter in both ranges. VDD must be lowered to 0.2 V in order to reset part.
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Product data sheet
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PCA9548A
8-channel I2C switch with reset
12. Dynamic characteristics
Table 8: Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus Min tPD fSCL tBUF tHD;STA propagation delay from SDA to SDn, or SCL to SCn SCL clock frequency bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock setup time for a repeated START condition setup time for STOP condition data hold time data setup time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line pulse width of spikes which must be suppressed by the input filter data valid time data valid acknowledge LOW-level reset time reset time (SDA clear) recovery time to START condition HIGH-to-LOW LOW-to-HIGH tVD;ACK RESET tw(rst)L trst tREC;STA
[1] [2] [3] [4]
[4] [4]
Fast-mode I2C-bus Min 0 1.3 0.6 Max 0.3 [1] 400 -
Unit
Max 0.3 [1] 100 -
0 4.7 4.0
ns kHz s s
tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tr tf Cb tSP tVD;DAT
4.7 4.0 4.7 4.0 0 [2] 250 4 500 0
3.45 1000 300 400 50 1 0.6 1 -
1.3 0.6 0.6 0.6 0 [2] 100 20 + 0.1Cb 20 + 0.1Cb 4 500 0
[3] [3]
0.9 300 300 400 50 1 0.6 1 -
s s s s s ns ns s s ns s s s ns ns ns
Pass gate propagation delay is calculated from the 20 typical Ron and the 15 pF load capacitance. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. Measurements taken with 1 k pull-up resistor and 50 pF load.
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Product data sheet
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
SDA tBUF tLOW SCL tr tf tHD;STA tSP
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
002aaa986
Fig 15. Definition of timing on the I2C-bus
START SCL
ACK or read cycle
SDA 30 % trst
RESET
50 % tREC;STA
50 % tw(rst)L
50 %
trst LEDx 50 % LED off
002aab174
Fig 16. Definition of RESET timing
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 (R/W)
acknowledge (A)
STOP condition (P)
1/f
SCL
SCL tBUF tr tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
Fig 17. I2C-bus timing diagram
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Product data sheet
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
13. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 18. Package outline SOT137-1 (SO24)
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Product data sheet
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 19. Package outline SOT355-1 (TSSOP24)
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Product data sheet
Rev. 01 -- 15 April 2005
19 of 25
Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
SOT616-1
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 e y1 C y
e 7 L 6
Eh
1/2 e
e2
1
18
terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 20. Package outline SOT616-1 (HVQFN24)
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Product data sheet
Rev. 01 -- 15 April 2005
20 of 25
Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
14. Soldering
14.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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Product data sheet
Rev. 01 -- 15 April 2005
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
14.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
14.5 Package related soldering information
Table 9: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
9397 750 13297
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Product data sheet
Rev. 01 -- 15 April 2005
22 of 25
Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
15. Abbreviations
Table 10: Acronym CDM ESD HBM IC LSB MM MSB PCB POR Abbreviations Description Charged Device Model Electro Static Discharge Human Body Model Integrated Circuit Least Significant Bit Machine Model Most Significant Bit Printed-Circuit Board Power-On Reset
16. Revision history
Table 11: Revision history Release date 20050415 Data sheet status Product data sheet Change notice Doc. number 9397 750 13297 Supersedes Document ID PCA9548A_1
9397 750 13297
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Product data sheet
Rev. 01 -- 15 April 2005
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Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
17. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
19. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
20. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13297
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 15 April 2005
24 of 25
Philips Semiconductors
PCA9548A
8-channel I2C switch with reset
21. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 8.5 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 Control register definition . . . . . . . . . . . . . . . . . 7 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 8 Characteristics of the I2C-bus. . . . . . . . . . . . . . 9 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 START and STOP conditions . . . . . . . . . . . . . . 9 System configuration . . . . . . . . . . . . . . . . . . . . 9 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11 Application design-in information . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 22 Package related soldering information . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information . . . . . . . . . . . . . . . . . . . . 24
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 15 April 2005 Document number: 9397 750 13297
Published in The Netherlands

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